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Although the theme of this request is consistent with our business strategy, it is not committed to the release that is currently under development.
Please see in addition some use cases in more verbose format:
As a physical designer (layouter) I need to find/see differences between my workspace (config spec set to e.g. label, branch, timestamp) and a workspace from schematic designer (config spec set to e.g. label, branch, latest..) (checked in data), so that I can plan, which layout cells need to be changed to get matched layout vs schematic status (clean LVS).
As a verification engineer I need to find/see differences between my workspace (config spec set to e.g. label, branch, timestamp) and a workspace from schematic designer (config spec set to e.g. label, branch, latest..) (checked in data), so that I can plan, which vhdl models need to be updated to be able to run the verification plan of schematic design.
As a project manager I need to find/see differences in design hierarchy (layout and schematic) between two derivates of a chip ( “TO1 and TO2 == label vs label”, or “TO1 and derivate of TO1 == label vs branch out of label” or “TO1 and current design== label vs latest” so that I can see if right blocks (version of blocks) will be taped out.
In all roles/scenarios I am interested in:
* Whole workspace (manager workspace) or
* Hierarchy only (manage hierarchy)